1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for fabricating the same, and more particularly to a dynamic random access memory (DRAM) device and a method for fabricating the same.
2. Description of the Prior Art
As semiconductor devices have a more improved integration degree, the fabrication thereof should satisfy more various requirements. Particularly, in DRAMs, the requirements for the high integration degree include an isolation between neighboring elements and an increase in capacitance.
Silicon-on-insulator (SOI) technique is one of techniques capable of easily providing an isolation between neighboring elements while improving characteristics of elements.
In accordance with techniques the SOI technique, a transistor is formed on a semiconductor layer disposed over an insulating layer. In the most general SOI structure, a silicon single crystalline layer is formed over a silicon oxide film.
FIG. 1 illustrates a conventional SOI transistor structure.
The SOI technique makes it possible to realize highly dense integrated circuits exhibiting high performance, because it reduces parasitic elements present in integrated circuits formed on bulk semiconductors.
In a MOS transistor formed on a bulk silicon substrate, a parasitic capacity is present between the substrate and source/drain regions. Also, there is a possibility that a breakdown phenomenon occurs at the source/drain regions and the substrate region.
Where a CMOS transistor is formed on a bulk silicon substrate, a latch-up phenomenon may occur at a parasitic bipolar transistor formed due to n-channel and p-channel transistors in neighboring wells.
On the other hand, the SOI structure can reduce considerably parasitic elements and increase a resistance force caused by a junction breakdown. In this regard, the SOI technique has been known as being suitable for fabrication of highly integrated devices with a high performance.
However, such a SOI structure has several problems caused by its lower insulating layer which is denoted by reference numeral 4 in FIG. 1.
In a bulk transistor which is denoted by reference numeral 1 in FIG. 1,, an, electrical connection is easily obtained by a body node 12 via a substrate 2.
The body node 12 is maintained at an electrically floated state, because it is insulated from the substrate 2 by the lower insulating layer 4.
Under a sufficient bias between a source 6 and a drain 8, majority carriers move to the body node 12, while minority carriers move to the drain 8. The movement of carriers causes an ion impact by which electron-hole pairs are generated at a region near the drain 8. As a result, a voltage difference occurs between the body node 12 and the source 6 of the transistor.
Such a voltage difference results in a decrease in effective threshold voltage and an increase in drain current. Consequently, a "kink" phenomenon occurs in the drain current-voltage characteristic.
In the SOI structure, there is also a problem that a parasitic "back channel" transistor is formed, which uses the substrate 2 as its gate and the lower insulating layer 4 as its gate insulating layer.
The parasitic "back channel" transistor causes the operation characteristic of transistor to be unstable.
In FIG. 1, the reference numeral 10 is a gate, 16 a gate side wall, and 18 an LDD junction region.
For achieving a high integration of DRAMs, the cell size of DRAMs must be reduced. Such a reduction in DRAM cell size results in a decrease in capacitor area.
However, the capacitor should have a capacitance large enough to generate a signal. Naturally, this requires a sufficiently increased capacitor area.
In this regard, there have been proposed various methods capable of obtaining a large capacitance even at a small capacitor area. One example is disclosed in U.S. Pat. No. 5,102,817. Now, a vertical DRAM cell structure disclosed in U.S. Pat. No. 5,102,817, will be described.
FIG. 2 is a sectional view of the vertical DRAM cell structure.
As shown in FIG..2, the DRAM cell is formed on a p type silicon substrate 32 over which an n well 34 is formed. The DRAM cell includes a field oxide film 36, an oxide film 38, a nitride film 40, a word line 14, a bit line 20, a bit line strap 24, a n.sup.+ capacitor plate region 44, a capacitor insulating oxide film 46, a capacitor plate 48, a transistor channel 58, a gate oxide film 56, and a buried isolation oxide film 52.
In this structure, a cell capacitor is constituted by the capacitor plate 48 and the n.sup.+ capacitor plate region 44. The oxide film 46 serves as a capacitor insulating film. Charges are stored in the capacitor plate 48.
A cell transistor is constituted by a source provided by the capacitor plate 48, a drain provided by the bit line 20, a channel provided by the polysilicon channel 58, a gate provided by the word line 14, and the gate oxide film 56.
The DRAM cell with the above-mentioned vertical structure has an advantage of a small occupied area per cell.
However, the structure .has at each trench side wall a single conductive layer Which has a uniform concentration throughout its length. The conductive layer has a lower portion constituting the capacitor plate 48 and an upper portion constituting the transistor channel 58. Since the single layer with the uniform concentration serves to achieve two functions, operation may become unstable.